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Add a new stage to generate zebin for XPU.

@chengjunlu chengjunlu changed the title Add a new stage to generate zebin to align CUDA stages in triton.compile [Draft] Add a new stage to generate zebin to align CUDA stages in triton.compile Sep 25, 2025
@chengjunlu chengjunlu force-pushed the chengjun/add_zebin_stage branch from 4cba65d to a943a26 Compare September 25, 2025 06:00
stages["ttgir"] = lambda src, metadata: self.gluon_to_ttgir(src, metadata, options)
stages["llir"] = lambda src, metadata: self.make_llir(src, metadata, options)
stages["spv"] = lambda src, metadata: self.make_spv(src, metadata, options, self.device_arch)
stages["zebin"] = lambda src, metadata: self.make_zebin(src, metadata, options, self.device_arch)
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We can't make this step mandatory yet (due to #5153 (comment)), but if we make it optional using options.generate_native_code, we can do a good refactoring right now.

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I refactor the code with options.generate_native_code. Please help to review the changes.

@etiotto etiotto requested a review from Copilot September 25, 2025 14:58
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Pull Request Overview

This PR adds a new "zebin" compilation stage for XPU backend to align with CUDA compilation stages in triton.compile. The change introduces zebin as a binary format alternative to SPIRV for Intel XPU targets.

  • Adds make_zebin method to generate zebin binary format from SPIRV input
  • Updates binary extension from "spv" to "zebin" for XPU backend
  • Modifies compilation pipeline to handle zebin as a binary format alongside cubin and hsaco

Reviewed Changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated 3 comments.

File Description
third_party/intel/backend/compiler.py Adds zebin compilation stage and updates binary extension
python/triton/compiler/compiler.py Updates file parsing and compilation pipeline to support zebin format

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Instead of using ocloc to generate the native binary, can we use L0 to generate it ?

How about trying: https://oneapi-src.github.io/level-zero-spec/level-zero/latest/core/PROG.html#module-caching-with-native-binaries

@etiotto etiotto marked this pull request as draft October 9, 2025 14:10
@chengjunlu chengjunlu force-pushed the chengjun/add_zebin_stage branch from a943a26 to c7cbf86 Compare October 29, 2025 03:32
@chengjunlu chengjunlu marked this pull request as ready for review October 29, 2025 03:32
@chengjunlu chengjunlu linked an issue Oct 29, 2025 that may be closed by this pull request
@chengjunlu chengjunlu force-pushed the chengjun/add_zebin_stage branch from c7cbf86 to f2186c2 Compare October 29, 2025 03:50
@chengjunlu chengjunlu changed the title [Draft] Add a new stage to generate zebin to align CUDA stages in triton.compile Add a new stage to generate zebin to align CUDA stages in triton.compile Oct 29, 2025
@chengjunlu chengjunlu force-pushed the chengjun/add_zebin_stage branch from f2186c2 to dabaee1 Compare October 29, 2025 04:28
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Instead of using ocloc to generate the native binary, can we use L0 to generate it ?

How about trying: https://oneapi-src.github.io/level-zero-spec/level-zero/latest/core/PROG.html#module-caching-with-native-binaries

It L0 API requires passing the device context which is not avaliable during triton.compile context.

@chengjunlu chengjunlu force-pushed the chengjun/add_zebin_stage branch 2 times, most recently from bbd3669 to b66f0b5 Compare October 29, 2025 07:13
size_t global_range_y = {gridY};
size_t global_range_z = {gridZ};
size_t local_range_x = {num_warps} * {threads_per_warp};
if (driver_version.find("+") != std::string::npos) {{
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This code doesn't make sense. Remove it.

… or option = {"generate_native_code": 1}.

Signed-off-by: Lu,Chengjun <[email protected]>
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